Netlist Tab

The Netlist tab creates and manages netlists for all cells.

The following tools are available in the Netlist tab:

• Create Netlist
• Netlist Connections
• Analyze Netlist
• Clear Netlists
• Select Net
• Active Nets
• Netlist Cell Instances
• Netlist Properties
• Logic Paths
• Short Finder
• Logic Block Search
• Check Netlists
• Find External Ports
• Find Transistors
• Identify by Truth Table
• Identify by Netlist

Create Netlist

Select the cell to netlist. For selecting a cell see: Project Cells Window

Click on the Create Netlist icon to bring up the window:

Select the desired layers. Typically diffusion and poly layers are only used in library cells and metal1 and above are used in larger cells that contain routing information.

Each instance of each cell can have it’s own netlist. Once the primary cell instance has been netlisted, the netlist command will run without asking for the layer connections. It will simply use the same layers selected for the primary instance.

If the cell instance already has a netlist the following message will appear:

Netlist Connections

Defines the connections in a netlist. The connections can be updated for the active netlist from here.

If updating a connection, a confirmation dialogue will appear.

For a brief description see: Netlist Connectivity

Analyze Netlist

When highlighted, the active netlist will be updated in real time. If the netlist is very large, it is reccommended that Analyze Netlist is off while editing.

To view the netlist, click the Active Nets icon.

Clear Netlists

Clears all netlists in the project.

Set analyze to Enabled to re create all netlists. Set to Disabled to keep all netlists empty.

Select Net

When highlighted, the select net tool will highlight a net in the active netlist. Click on the polygon in the overlay window to highlight nets in red.

To change the default color see selected net in Preferences

Active Nets

When highlighted, the Active Nets window is open. It will be a tab under the overlay.

Nets highlighted in the overlay will be selected in the Active Nets netlist. The left pane of the Active Nets window contains the net id, name, number of ports, number of polygons, error state, net type, and errors. The right pane of the Active Nets window lists all of the ports and cell information connected to the highlighted net.

The outline mode icon controls the selected net outline mode. Default is to show the net with the layers filled in. When depressed, only the selected net outline is shown.

The ignore errors icon ignores any errors on the selected net. The purpose is to give the user a marker for nets visited that have false errors being reported.

The add filter icon filters out the nets by column and parameters set in the window:

The left window contains the list of nets. Here are the columns:

• Net: The name of the net.
• Ports: The number of ports in the net.
• Polygons: The number of polygons in the net.
• State: A green checkmark indicates no errors. A red x indicates at least one error.
• Error: A short description of the net’s error.

If you click on a row, then the camera will zoom to the net and highlight it, and the right window will show the details of the selected net.

The right window contains the list of ports for the currently selected net. Here are the columns:

• Cell Number: The number of the port’s cell.
• Cell: The name of the port’s cell.
• Instance: The name of the port’s instance.
• Port: The name of the port.
• Type: The port type: Input, Output, Inout, VSS, or VDD.

If you click on the right column, then the camera will zoom to that particular port.

Netlist Cell Instances

The Netlist Cell Instances window will open in the bottom pane.

Click on the magnifying glass to search for a particular instance in the netlist. The overlay camera will zoom to the instance.

Click on the wand to annotate cell instances using the desired convention.

Netlist Properties

When highlighted, the Active Netlist Properties menu opens. Choose between the following options:

The Netlist window shows the active netlist in various formats. Choose the format from the drop down menu. Formats include component verilog, functional verilog, SPICE, VHDL, and comma-separated values.

The Schematic Image is populated when a reference cell match is found. The schematic is stored in the Reference Cell Library.

The Schematic shows the automatically generated schematic. For more information see Schematic Tab and Schematic Tool Basics.

The Truth Table is the automatically created truth table of the circuit.

Logic Paths

Opens the Logic Paths window (tab) in the lower left:

Click the plus sign to add highlighted nets to the Logic Paths list. The net will stay highlighted in the overlay in the desired color as long as the net is checked allowing the user to view multiple nets at a time.

click on the to open the input dialogue. Setting increasing values allows the user to follow a signal through all of the cells it is an input to.

The green net is the original net, and the blue nets are the level 1 descendent nets.

Note: The paths created will not be saved when you close Pix2Net.

Short Finder

The shortfinder window opens in the lower left corner:

Select a port that is part of the short then click set. Select the second port and click set. Click Update Path. The shortest path between the 2 ports is highlighted.

Logic Block Search

Clicking on Logic Block Search opens the following window in the bottom pane:

Clicking on the magnifying glass allows the user to search for logic blocks.

The Logic Block Search Settings window pops up:

It is pre-populated with the last search performed. To search this again, click search.

The icons in the top of the window allow for different search types. Pix2Net will retrieve the block information from the Logic Paths window , the current selected cells , or from a verilog file .

When loading from the Logic Paths window, the pattern traced by all of the nets in the window will be used.

The first example is retrieving logic blocks from the Logic Paths window. Below is an example of a highlighted net that is populated in the Logic Paths window.

Click on the magnifying glass and then click on the first icon to get the pattern from the logic paths. The logic path will load in the window:

Click on the search button. All similar blocks are now highlighted in the overlay, and the logic block search window shows them as well.

The search block can be cleared by clicking clear results icon. The user can save the current block search by clicking the save icon in the Logic Block Search Window. This will pop up a dialog that will allow the user to enter a name for the block to be saved. Note that currently Pix2Net allows the user to save blocks with the same name without a warning. The user can also load a saved patter by clicking on the Load Pattern icon.

Check Netlists

The following check netlist options are avaliable:

Check for invalid source-drain order will verify that each transistor is oriented with the source tied to VDD/VSS.

Fix invalid source-drain order will automatically orient any of the invalid orders found in the check. Run the check and fix when comparison tools do not allow source and drain to be interchangeable.

Check instance consistency verifies that the netlist of each instance of a cell matches the primary instance netlist. This will compare the instances of all checked cells in the right hand pane and will report a match to a different, checked cell if there is an inconsistency.

Check database consistency verifies that the netlist doesn’t have any missing entries in the database that could cause problems or inconsistencies in the netlist. Run this periodically if database inconsistencies or corruption are suspected.

To access the reports created, got to the View tab and click on the Reports button. This will open the reports in the bottom of the GUI.

Find External Ports

Finding external ports will find all ports that enter or leave the selected cell. with the exception of the top cell.

Options for placing the ports are listed in the FInd External Ports window.

Find Transistors

Finds transistors in the selected cell. If transistors exist in the cell, Pix2Net will ask for confirmation before deleting the current transistors and placing new ones.

Identify by Truth Table

This will open the Identify By Truth Table window in the bottom pane.

To set the library of comparison, click the wrench. A drop down menu will appear:

After selecting the desired library, click the magnifying glass to run the comparison to the active netlist. A list of possible matches will appear:

The score shows the percentage of match. A 100% is the best possible.

Select one of the 100, and click on the green check mark to check it in. The truth tables show how the signals will map. The Cell Identified window will pop up.

Click copy to transfer the checked properties to the current cell. If the user finds a cell that is not in the library, the cell can be added to the library by clicking on the book icon.A confirmation dialog will pop up:

Identify by Netlist

This will open the Identify by Netlist window in the bottom pane.

Set the reference library as done in the Identify by Truth Table, click on the magnifying glass to run the compare:

The comparison with the highest score is the closest match. If one (or more) has 100, that is a perfect match. Click on the green check mark to check it in, or on the book if you have found a new cell you would like to add to the library.