Project Cells Window

Project Cells Reference


The project cells window also allows you to toggle the following windows:

The project cells window shows all of the cells in the project in a tree. You can toggle the visibility of a cell in the tree by clicking on its checkbox. Right-click a cell to bring up the context menu:

  • Show [cell] Only: Equivalent to selecting this cell’s check box, and deselecting the check box of every other cell.
  • Show [cell] and Children Only: Shows this cell and is children, and hides the other cells.
  • Show to Level...: Shows all of the cells in the hierarchy to the given level.
  • Show All: Equivalent to selecting every check box.
  • Hide All: Equivalent to deselecting every check box.
  • Rename [cell]: Renames the cell.
  • Delete [cell]: Removes the cell, including its instances and ports.
  • Delete Children: Deletes only the child cells of the selected cell.
  • Electrical properties: Opens the electrical properties of a cell. Currently, these properties must be manually entered.
  • Set as Active Section: Sets the highlighted section as the active one. Only applies to Sections not Cells.

Cell Netlist


The cell netlist browser allows you to view the netlist of a selected cell. Generally there is only one netlist per cell instance. If more than one netlist exists for a given cell you can see if any variations exists. Only one active netlist is allowed and all netlist commands will only affect

Cell Instances


The cell instances window allows you to see the instances and ports of the cell currently selected in the Project Cells window. When you select an instance in the table, the camera in the layer window will center on the instance and highlight it with a blue box.

The instances table has the following columns:

  • Instance: The instance number.
  • Name: The instance’s name. This field is editable.
  • Parent: The instance name of the parent cell.
  • Parent Cell: The name of the parent cell instance.
  • Lower Left: The lower left corner of the cell boundary in microns.
  • Correlation: A number from 0 to 100 that represents how similar this instance is to the original cell image.
  • Orientation: The instance’s orientation: Normal, Flipped Up-Down, Flipped Left-Right, or Rotated 180 degrees.

The ports table has the following columns:

  • Port: The name of the port.
  • Type: The port’s type: Input, Output, or Inout.
  • Layer: The layer the port was placed on.

Flat Cell List


The flat cell list window shows you a flattened list of all of the cells in the project. The following columns are displayed:

  • Name: The name of the cell.
  • ID: The id associated with the cell.
  • Instances: The number of cell instances.
  • Electrical Type: The electrical properties associated with the cell.
  • Nets: The number of nets in the transistor netlist (if the cell has a transistor netlist).
  • Section: Indicates whether or not the cell is a section.

Project Cell Netlist Properties

Reference Cells


The reference cells window displays the cells in the reference library. Currently, if you change the reference library.

The displayed columns are similar to the ones in the Project cells window.

Reference Cell Netlist Properties

These properties are very similar to the Project cell properties, except that it shows the selected reference cell, instead of the selected project cell. Also, reference cells do not store transistor widths and lengths.

Search Plans


The Search Plan pops up as a tab in the lower left of the GUI. The green plus creates a new search plan. The red x deletes the highlighted plan. The wrench changes settings to the highlighted plan. The play button will execute the highlighted plan across the entire image space. The note pad opens the highlighted search plan that has been executed, but not committed meaning the cells have been placed in the overlay.

The add or edit button will pop up the following menu:


  • Layers: Check the layers to include in the search.
  • Cells: Click the green plus to add cells. Click the red x to remove the highlighted cell from the search.
  • Minimum Correlation: This number determines how strict the search will be as it looks for this cell. The higher the number, the more closely the candidate instance must match the original instance in order to be considered a successful match.
  • Maximum Correlation Difference: the maximum allowed difference between the correlations of overlapping results. For example, let’s say you get three results that happen to be overlapping, and thus, they can’t all be valid matches. The correlations of the three results are 92%, 85%, and 80%. If you set the maximum difference to 10%, then the 92% and 85% results will be shown to the user, but the 80% result will be automatically discarded, because it is less than 82% (92% - 10% = 82%).
  • Maximum Allowed Overlap: This is the maximum distance two cell boundaries are allowed to overlap. Make sure this number is smaller than the width of the smallest cell in the project.
  • Use Active Netlist to Filter Results: Check this to use the active netlist, typically the top netlist, to aid in filtering the results. This feature is especaily useful for placing cells in gate arrays where the pmos and nmos transistors are the same size.
  • Properties: The user can set crop values for the purpose of honing the search better. Zoom in/out is allowed for the cell view. The arrow buttons will cycle through to pick the particular instance of the cell to be used for matching.
  • Anchor point:Draw an anchor point to help with cell placement by left clicking and dragging across a feature to key off of on the desired layer. A red box will indicate the anchor point.

Be sure to press Ok to save changes made in the Edit Search Plan Settings window.

The note pad button pops up the Confirm Search Plan Results window. This window also pops up after running Area Search.


  • Placements: Lists the number of cell placements found in the last search.
  • Confirmed: Lists the number of placements that have been accepted (green checkmark).
  • Unvisited: Lists the number of cell placements that have not yet been reviewed.
  • Green Check: Confirms all selected cell in the list. The short cut key is 1.
  • Red X: Eliminates all selected cells as possible placements. The short cut key is 0.
  • Up: Selects everything above the currently selected cell.
  • Down: Selects everything below the currently selected cell.
  • Skull: Eliminates all results of the current search without placing any cells.
  • User can zoom in/out, and also chose to widen the view by selecting Show Context.

Cell Identification

See the tutorial: Identify Cells by Truth Table

Add/Edit Port


This dialog allows you to add a new port or edit an existing one. The following properties are displayed:

  • Cell - The cell the port belongs to.
  • Instance - The cell instance the port belongs to.
  • Hierarchy - This is Normal for most ports, External for ports that belong to the top cell instance, and Intermediate for ports that have been automatically added during the netlisting process.
  • Net - The net the port belongs to, or none if the port has not been netlisted.
  • Location - The location of the port.

You can edit the following properties:

  • Name - The name of the port.
  • Layer - The layer the port belongs to.
  • Type - The port type: Input, Output, etc.

Confirm Identification


This dialog allows you to choose how the target cell is synchronized to the reference cell. You can choose to copy the cell name, the transistor names, and the port names from the reference cell to the target cell. The port types and schematic from the reference cell will also be copied over when you click the Confirm button.

Electrical Properties

Here’s a little bit about electrical properties.

No Type


This is the default state for all new cells. Hierarchical cells that contain other components will have this state. It has no properties.



<Add image of a resistor component>

Length: <Add definition>

Width: <Add definition>

Sheet Resist: <Add definition>

calculator (All Types)

sheetResist = \frac{width}{length} \times totalResist

Total Resist: <Add definition>

calculator (All Types)

totalResist = \frac{length}{width} \times sheetResist



<Add image of a capacitor component>

Length: <Add definition>

Width: <Add definition>

Unit Capacitance: <Add definition>

calculator (MIM)

unitCapacitance = \frac{totalCapacitance}{length \times width} \times 1.0\e{-15}

calculator (Dual MIM)

unitCapacitance = (\frac{totalCapacitance}{length \times width} ) + (length \times 2.0) + (width \times 6.0)) \times 1.0\e{-15}

calculator (DCAP)

unitCapacitance = \frac{totalCapacitance}{length \times width} \times 1.0\e{-15}

Total Capacitance: <Add definition>

calculator (MIM)

totalCapacitance = width \times length \times unitCapacitance \times 1.0\e{-15}

calculator (Dual MIM)

totalCapacitance = ((width \times length) + (length \times 2.0) + (width \times 6.0)) \times unitCapacitance \times 1.0\e{-15}

calculator (DCAP)

totalCapacitance = width \times length \times unitCapacitance \times 1.0\e{-15}



<Add image of BJT component>

Length: <Add definition>

Width: <Add definition>

Vth: <Add definition>

Area: <Add definition>

calculator (All Types)

area = length \times width



<Add image of MOSFET component>

Length: <Add definition>

Width: <Add definition>

Fingers: <Add definition>

Vth: <Add definition>

Total Width: <Add definition>

calculator (All Types)

totalWidth = width \times fingers

Source Length: <Add definition>

Source Width: <Add definition>

Source Area: <Add definition>

calculator (All Types)

sourceArea = sourceLength \times sourceWidth

Source Perimeter: <Add definition>

calculator (All Types)

sourcePerimeter = (sourceLength \times 2.0) + (sourceWidth \times 2.0)

Drain Length: <Add definition>

Drain Width: <Add definition>

Drain Area: <Add definition>

calculator (All Types)

drainArea = drainLength \times drainWidth

Drain Perimeter: <Add definition>

calculator (All Types)

drainPerimeter = (drainLength \times 2.0) + (drainWidth \times 2.0)



<Add image of inductor component>

Outer Diameter: <Add definition>

Inner Diameter: <Add definition>

Number of Turns: <Add definition>

Inductance: <Add definition>

calculator (Octagon)

&A = 1.07 \\
&B = 2.29 \\
&C = 0.0 \\
&D = 0.19 \\
&\mu = 4\pi \times 1.0\e{-6}\\
&d_{avg} = \frac{(outDiameter + inDiameter)}{2.0}\\
&\rho = \frac{(outDiameter - inDiameter)}{(outDiameter + inDiameter)} \times 1.0\\
&inductance = \mu \times numTurns^2 \times d_{avg} \times A \times (\log(\frac{B}{\rho}) + (C\rho) + (D\rho^2))



<Add image of diode component>

Length: <Add definition>

Width: <Add definition>

Number of Anodes: <Add definition>

Area: <Add definition>

calculator (All Types)

area = length \times width

Unit Capacitance: <Add definition>

calculator (All Types)

unitCapacitance = \frac{totalCapacitance}{length \times width \times numAnodes} \times 1.0\e{-15}

Total Capacitance: <Add definition>

calculator (All Types)

totalCapacitance = width \times length \times numAnodes \times unitCapacitance \times 1.0\e{-15}



This cell type is used to denote an area that contains bits for memory extraction. It has no properties.