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- Improved FEI MAPS import feature to use the included stitch information, if present.
- Transistor symbols in the schematic will now report measurements in nanometers, if necessary.
- Fixed a bug in the image filter system which caused it to always emit greyscale images, which in turn caused rendering errors after performing a partial-layer filter on a layer with color images.
- Added a system to allow ribbon tools to insert items in the right-click context menu in the overlay.
- Updated the add/erase line tools to perform multi-point input by default. Circuit traces are now much more easy to fill in using the add line tool. To stop adding lines: press escape, change the active tool, or use the right-click menu. The thickness can still be changed with ctrl, and the line can still be angle-locked with shift.
- Updated the add polygon, erase polygon, and freeform area select tools to be able to undo previously placed vertices without cancelling the entire shape. Ctrl-click or use the right-click menu to remove the most recent vertex.
- Fixed a bug in the schematic system which could cause transmission gates to not display the correct symbol.
- Fixed a bug which could prevent the Huntron proper feature from working properly with layers which had been imported, rather than being captured by Pix2Net.
- Fixed a bug in the CSV netlist exporter which caused it to not fully descend into the cell hierarchy under some circumstances.
- Fixed a bug in the view-only version which could cause it to not properly initialize a subsystem, leading to an error message.
- Fixed a bug in the schematic export system which could cause incorrect cell type names to be written in the protected version.
- Fixed a bug in the Beam Control system which could cause an error when starting a new capture under certain conditions.
- Added the option for the "complete netlist" export feature to only include library cells which are actually involved in the netlist to be exported.
- Added the option for the "complete netlist" export feature to follow schematic block structure.
- When writing functional Verilog, cells which fail for any reason will now write a dummy cell in addition to the error message.
- Renamed "H Functional Verilog" to "Human-Supplied Functional Verilog" for better clarity on the feature’s purpose.
- When writing functional Verilog, simulation and automated Verilog generation will no longer be attempted for netlists which have human-supplied functional Verilog. The human-supplied code will be used instead.
- Project synchronization IDs are now required. This only matters for very old projects which were created before the release of the sync system, and these projects will automatically be upgraded to ensure that they are assigned an ID.
- Fixed a bug that could cause issues with fresh Pix2Net installations.
- Updated archive system to tolerate missing archive directory. Updated archive restore process to handle stub gracefully.
- Improved clarity of archive warning messages. Raised threshold for delta file size warning message from 500MB to 5GB.
- Fixed a bug in the netlist and area 3D visualizer which could fail upon encountering an invalid polygon.
- Added a Beam Control feature to the capture system. Using the settings menu in the capture configuration window, Pix2Net can now enable/disable the SEM beam before/after the capture.
- Fixed a bug in the Gerber exporter which would create empty files for layers with no modules. Now, only layers containing at least one module will get a Gerber file during generation.
- Integrated with the first internal release of the new stitch system. This system is currently undergoing internal testing, and will be made functional in release versions soon.
- Fixed bug in multiple image importer that caused a failure when using column-first ordering on an import with unequal rows/cols.
- Added many new KiCad modules to the default module package.
- Fixed a bug in the sync system which could cause errors when one satellite project renamed or resized a cell which had been deleted by another satellite project.
- Added a new Adjust Clipboard command to the Microscope Control system, to support focus adjustment on the Zeiss Merlin SEM.
- Upgraded Pix2Net Server to v1.08 to support the new Adjust Clipboard command. The Pix2Net Server component should be replaced with the included version on any capture machines after this version is installed.
- Fixed a bug in the DBv88 upgrader.
- Removed the featureless tile detection system while we investigate issues it has caused with memory management and trend line analyzer performance.
- Added the ability to delete cells directly from the Active Nets window's port pane.
- Fixed several bugs related to the stitch viewer and the featureless tile detection system.
- Added description text to the command history window for commands which add cell instances (including commit cell search placements).
- Fixed a bug in the command history display of the Add Port command which could cause an error when attempting to create a clickable location link.
- Added the ability to select row-first or col-first ordering when importing single-indexed images.
- Added an option in the stitch settings window to disable the new featureless tile detection system, for layers where it causes problems.
- Added support for rotated pads in custom KiCad modules.
- Fixed bug in the image import system that could cause an error message when an import job with the “allow gaps” option enabled was missing the first image in the set.
- Fixed a bug in the module system that could cause errors to be displayed under certain circumstances when loading the module list.
- Fixed a bug in the external port finder which could cause a silent error if the netlisting process was incomplete for the containing netlist.
- "Show polygons" in the extraction preview window now defaults to disabled. Defaulting to enabled impacted the user experience when filters had not yet been tuned for a layer, and during capture preview.
- Fixed a bug in the sync system which prevented the restore backup protections from working correctly, which could in turn cause damage to a project in certain situations.
- Fixed a bug in the cell renderer that dramatically slowed down all rendering in projects with many cells.
- Fixed a bug that prevented the minimum hole size setting from being saved properly.
- Added support for KiCad modules with rounded rectangle pads.
- Added show/hide-all buttons for image and polygon layers in the layers window.
- Added detection of featureless regions to the stitcher. Tiles with no useful stitch information will no longer be treated with the same weight as regular tiles when performing trend line fitting.
- Added the option to select which stages to run when starting a stitch process.
- Added more helpful messages to several error conditions associated with neural networking.
- Tweaked the Select Net took to favor nets with polygons on visible layers. These nets will be selected before others when clicking multiple times to cycle through the nets.
- In the polygon extraction process, made the “minimum hole size” value a user-configurable setting.
- Fixed bug in the multiple image import process which caused errors when both cropping and splitting.
- The Identify Cell feature will now automatically assign the correct electrical model, if it is able to determine it.
- Improved the logic behind importing custom module types. Pix2Net will now have a better chance of assigning the correct types to the specified ports.
- Fixed a GPU memory leak bug in the cell renderer system which caused periodic JVM crashes when performing many cell-related operations.
- Fixed bugs in the ODB++ exporter which caused it to fail when running the protected version of Pix2Net.
- Fixed bug in Raith RAW image import which caused it to fail for images with at least one dimension larger than 32,768 pixels.
- Changed the way that cell search key points are generated and stored. Setting an auto key point layer after adding cells to a search plan will no longer fail to create the proper key points.
- Port name, type, and layer may now be edited using the port table in the cell instances window.
- Improved the error messages in the ODB++ Export system to convey more helpful information.
- Removed a restriction against schematics with more than 10,000 nets being routed.
- Fixed a bug in the default port name system which could cause an error message when creating certain types of cells.
- Fixed a bug in the cell search system which could cause the state of the “Use GPU” option to not be remembered.
- Fixed a bug in the cell search system which could cause errors when performing an area search in non-GPU mode.
- Added an Extraction Preview button to the Image tab. Allows the use of the extraction preview system with a selected file, rather than just through the camera system.
- Changed the stitcher GUI elements to present "maximum slice size" as a more intuitive "number of slices" instead.
- Added Schottky Transistor to the default electrical models.
- Fixed a bug with the polygon extraction window which caused the incorrect preview tile to be loaded on layers which had transformations applied.
- Added full support for Raith RAW images, and incorporated it into the usual import process.
- Added error detection for Raith RAW images. Correct errors will now be displayed for unexpected file size and missing header ID.
- Added STL export of any mesh displayed in the 3D viewer. Access this command via the right-click context menu in the viewer.
- Added scroll wheel zoom support to the 3D viewer.
- Fixed a bug which could prevent a test capture image from being displayed on a project with no image layers.
- Fixed a bug which could prevent a project from closing properly shortly after the extraction window was closed.
- Added layer thickness settings to the Technology window. These settings are obeyed by the 3D viewer tools.
- Module port types are now given a default setting by name, where possible.
- Fixed a bug with cell search that could cause the minimum score setting to be ignored under certain circumstances.
- Added basic support for D-code writing in Gerber export.
- Fixed a bug with custom module assignment which could cause imported modules to fail to load under certain circumstances.
- Added a new default electrical type “polarized capacitor,” with associated electrical properties.
- Expanded 3D netlist feature to be able to create 3D visualizations of the full stackup for any rectangular region.
- Created an undo/redo system for the Neural Network Training Set Editor window. Ctrl-Z and Ctrl-Y shortcut keys will now work as expected in this window.
- Updated the Pix2Net manual.
- Changed the polygon extraction preview window to optionally use a subset of tile images for extraction preview, for a better experience with very large tiles.
- The image clone process now runs in the Pix2Net task manager, with a progress bar.
- Fixed a bug that could cause an unhelpful error message when failing to open a project under certain circumstances.
- Added stitcher support for single-row image layers.
- Added the ability to import custom module files directly into a Pix2Net project. Imported modules will be shared during project synchronization.
- Updated FEI import feature to support files with multiple image sets for a single layer.
- Fixed the positioning of the overlay preview when placing modules.
- Fixed a bug that caused an error when browsing for a project in the recovery manager without a currently open project.
- Added a Spectrometer Calibration feature, which makes it easier to setup spectrometer capture runs using a small USB camera.
- Updated Sentinel HASP installer to v7.63.
- Made many improvements to the 3D spectrum feature system to make the structures more accurate and faster to generate.
- Captured spectrometer data is now stored differently. Spectrum layer load times are greatly reduced.
- Images being added to neural network training sets are now pre-loaded with the extracted preview polygons, if they are available. Previously, the filtered image would be used regardless of preview polygon availability.
- The Overlapping Tile Export feature will now use the warped images, if they are available.
- 3D spectrum structures can now have their visibility toggled properly.
- Upgraded neural networking libraries for improved functionality.
- Module pads now render correctly within nested rotated cells.
- Fixed a bug in the Gerber export which caused improper reuse of filenames and prevented correct results. Exported modules will now be saved with the suffix “_module” added to their filenames.
- JPG images generated by Pix2Net will now default to 85% quality instead of 95% quality, saving on file size and processing time without compromising correctness or apparent fidelity. The file format used can be selected in the Image Settings menu. PNG is still the default, though JPG may become the default in a future release.
- Made user experience improvements and bugfixes to the Grid of Ports tool.
- The Filter Layer feature can now optionally replace the original layer images. This setting is disabled by default and is gated by a conspicuous warning message.
- Neural network processing and training image creation now correctly bypass the image filter system.
- Neural network output can now be viewed in the Extraction Preview dialog.
- The neural networking feature can now operate on color images.
- Fixed error message upon clicking “Open Project” after running the create archive operation following an unclean shutdown.
- Added a histogram equalization filter, to help balance image layers with inconsistent brightness and contrast across their images.
- Improved support for configuration of Raith SEMs. The Raith remote user profile can now be set within Pix2Net before connecting to the device.
- The spectrum 3D surface system now respects the active IIR filter, if one is set.
- Cell module rendering options have been moved to a more intuitive location in the interface.
- Improved EDIF export for flat netlists and for import by Mentor Graphics.
- Fixed a bug in the Golden Lib GDS system which prevented it from working properly under some circumstances.
- Fixed a bug in the cell search system which could cause an error when saving new settings.
- Fixed ArrayOutOfBoundsException when trying to display a schematic containing a transmission block that isn't connected to anything on one or both sides.
- Fixed issues with well polygon connectivity when using automatically detected four-terminal transistors in a netlist.
- Made a change to the automatic transistor finder. When editing poly and active polygon layers in such a way that previously auto-located transistors will be adjusted, the transistors will be resized instead of recreated. This will prevent any schematic symbol involving the resized transistor from having its location reset.
- Further improved consistency in remembering last-used export locations.
- Introduced a simplified interface for the cell search settings menu, offering presets for low, medium, and high quality images, and two customizable slots.
- Fixed a bug that could cause ports to appear in the wrong location when a module is assigned to a cell.
- The "place components using physical locations" schematic feature is no longer restricted to schematics in manual mode with only physical cells.
- Pix2Net Server now supports multiple monitors on the controlled PC.
- Fixed position of the recovery system's custom time dialog.
- Improved port assignment logic when placing KiCAD modules.
- Improved consistency in remembering last-used export locations.
- Fixed a bug which caused an error under some circumstances when viewing schematics containing capacitors or resistors with blank capacitance or resistance properties.
- The capacitor electrical properties added to the reference library in v1.09.90 are now added to existing projects, eliminating the need to import and swap electrical models.
- The Length and Width electrical properties of several electrical models have been flagged as measurable. This applies to the reference library as well as to existing projects.
- Many export features have been updated to remember the last file path used for the export.
- The default Capacitor electrical type in the reference library now comes with electrical properties for Length, Width, Capacitance, and Unit Capacitance. Existing projects must import this type to make use of it. New projects will auto-import it.
- Capacitors now display their capacitance values in schematics. This feature can be toggled on and off in the schematic context menu.
- Resistors now display their resistivity values in schematics. This feature can be toggled on and off in the schematic context menu.
- Electrical properties can now be assigned a “measurability type.” Measurable properties will show a “measure” button in the edit electrical model window, alongside existing “calculate” buttons for properties with formulas. Clicking the measure button will fill the box with the associated measurement from the cell. The initial measurable types are the cell’s area, large dimension, and small dimension. Capacitor properties Length and Width are now measurable by default.
- Added 3D view capability to netlists and spectrum capture layers. Netlists and spectrum captures can now show a 3D visualization of the structures by using new buttons in the ribbon menu.
- Modified the "Place components using physical locations" schematic feature to place ports near their connected cells.
- Fixed bugs in the EDIF export process.
- Fixed a bug in the cell visibility system that caused error messages upon the creation of new cells.
- Added support for GDSII array reference data structures, which allows for correct import of GDSII files using this feature.
- Fixed a bug in the GDSII import process which could place polygons in the incorrect location when their reference had been mirrored.
- Added a new “Display Cells” option to the context menu for the layers window, which sets the current cell visibility quick filter to show all cells with ports on the specified layer.
- The export of Gerber modules is now based on the image layer rather than cell hierarchy.
- Removed the restriction against including non-library cells in a cell search.
- Updated the Gerber export system to include module information.
- When exporting cell instance information, the footprint module name and footprint library name are now available fields.
- EDIF export now includes module footprint information, if available.
- Fixed oversight in schematic system that prevented the "Place Components Using Physical Locations" feature from working if the schematic included any transistors created by the automatic transistor finder.
- Fixed bug in the PolygonExtractor which caused an error when extracting polygons from a single image taken by the Manual Move Panel.
- Fixed bug in the flat hierarchy export system which prevented it from working as expected.
- Updated the official Pix2Net manual with new information and examples.
- Fixed a bug with the polygon extraction which could cause it to run out of memory on projects with very complex tiles.
- Fixed a bug with the schematic system which could cause transistors to display the incorrect length and width values under some circumstances.
- Made improvements to the neural networking subsystems for bugfixes and improved performance.
- Fixed Huntron Dual Beam Prober integration issues.
- The cell search feature can now search on polygon layers in addition to image layers. The minimum score should be lowered when searching on a polygon layer (try starting at 80.0). An upcoming feature release should simplify the use of these settings.
- Added a customizable grid overlay system to assist with pitch and scale correction of devices. To enable, click the settings button in the polygon ribbon. While active, polygon operations will also snap to the grid points.
- Made updates to the PCB prober device server software for better performance and user experience.
- Fixed bugs in the schematic system which could cause the position and orientation of schematic symbols to not be preserved on netlist changes.
- Fixed a bug in the polygon operation system which prevented some polygons on a layer from being considered if that layer contained an especially large polygon.
- Fixed a bug in the Alignment Move tool which caused problems when changing the zoom level during a move.
- Changed golden compare to work better with via layers. Previously, it could miss extra metal differences in regions with no golden polygons.
- Fixed bugs in the EDIF export feature which caused hierarchical ports to be written incorrectly and some incorrect formatting to be used.
- Added "copy to layer" feature in the polygon context menu, to supplement "move to layer" feature.
- Fixed various errors in the EDIF export feature which caused improper display in some viewing software.
- Fixed multiple bugs in the EDIF exporter:
- The schematic pages are now associated with the correct cells (instead of the top cell containing all of the pages).
- The schematic cells are now ordered from child-to-parent, so that children appear before the parents.
- Instance numbers are now unique.
- Cells mirrored about the Y-axis are now positioned correctly.
- The EDIF cell names are now generated from the existing cell/port names.
- Fixed a bug in the freeform area selection tool which caused it to accidentally obey the maximum polygon size rules for its selection polygon.
- Fixed a bug in the cell search feature which could cause an error message when searching for rotated cells in a rectangular search area.
- Added a Bill of Materials feature to the export system, for PCB projects.
- Added an Add Line tool to the neural network training image editor.
- Fixed a bug in the Verilog generation system that prevented proper detection of output columns that are simple clones of other columns.
- Moved the state table control panel to the bottom of the window, so that it is not covered by the error display when it is visible.
- Added tools to allow addition and erasure of circle-shaped regions in the neural network training image editor.
- Fixed a bug that prevented Pix2Net Server from properly using a “floating image” resource once it had been defined in the Setup Server menu.
- Fixed a bug that caused an erroneous message in the Application Log window any time a connection to the Pix2Net Server was closed.
- Added an option to the cell annotation feature to allow annotation of every cell in the project, rather than only the active netlist.
- The cell instances window now shows the KiCad module for the cell being displayed, if it has one.
- When using the Edit Ports feature with multiple ports selected, changes made in the dialog will now be applied to all selected ports.
- Added better error messages when there are problems adding cells.
- Fixed bugs related to the automatic placement of ports when using the KiCad module system.
- Added new options to the cell settings menu. Cells which have a KiCad module assigned may now optionally be shown with their cell bounds and actual port locations, which would normally be hidden in favor of the module symbol.
- Fixed a bug that prevented KiCad modules from being previewed correctly in the overlay in some cases when selecting other modules in the Edit Module dialog.
- Fixed a bug that caused premature auto-alignment when adding new anchors in inter-layer alignment mode. On PCB projects, this could cause the layer to be resized or moved in such a way that it could not easily be recovered.
- Fixed a bug that caused alignment in layer-straightening mode to work improperly on PCB projects.
- Added new polygon tools to add and erase circles. These new tools use an approximation of a circle with a radius set in the polygon settings menu. As with the square and line tools, ctrl-clicking with the circle tool allows a second click to easily set a new radius without using the settings menu.
- Fixed a bug with cell creation that was introduced in the previous version.
- Added support for writing Excellon drill files when exporting PCB projects to Gerber format.
- Various fixes for KiCad module support.
- Hotfix to support a field installation.
- Various bugfixes and refinements for PCB reverse engineering features.
- Test release for internal use.
- Improved the appearance and functionality of the Gerber file export panel.
- Improved the accuracy and reliability of polygon extraction features.
- Added early support for the designation of cells as KiCad modules, for PCB reverse engineering.
- Added early support for grid-aligned placement of cells and polygons.
- Enabled the PCB ribbon tab until a proper separation of features across Pix2Net packages can be implemented.
- Updated the license management software to the latest version.
- Fixed a bug in Identify Cell which could cause the feature to fail to update net names, which causes problems for the State Table window and the SPICE export feature.
- Fixed a bug in the transistor detector which could cause detection to fail if a 3-terminal transistor did not appear over a well.
- Improved polygon generation and smoothing features, for better and more consistent creation of polygons from detected edges.
- The automatic transistor finder can now add 4-terminal transistors, and will place the bulk port on the underlying well layer. This feature must be enabled on a per-netlist basis.
- In the Project Properties window, users can now change the units used for the Micron Ruler tool. Users can select between automatic mode (the old method) or a specific unit.
- Combined transistors can now show transistor dimensions in schematics. If available, a combined transistor will use the dimensions from one of the child transistors which make it up.
- Fixed a bug that could cause the placing of cell search results, under certain circumstances, to create an illegal loop in the cell graph.
- Changed the default value for the stitching pass 1 setting "Correlation Margin" from 1% to 0.1%, which has proven to generate better results on most layers.
- The assign shortcut window now displays the name of the command to which the shortcut will be assigned.
- Fixed a bug in the import layer dialog which prevented the ignore prefix from working properly.
- Updated the Pix2Net manual.
- Fixed a bug which could cause errors when attempting to display a schematic for a cell in the reference library.
- Fixed a bug which caused an incomplete copy to the reference library when copying cells which contain transistors created by the automatic transistor finder.
- Fixed bugs in the neural networking system related to via detection.
- Fixed a bug in the Library Cell Catalog export feature which could cause errors when exporting cells without a primary netlisted instance.
- Added options to Library Cell Catalog export to allow for selective exclusion of cell image, schematic image, and Verilog.
- Updated the Pix2Net manual.
- Export of library cells in SPICE format will no longer list duplicate VSS or VDD ports.
- Fixed a bug in the schematic rendering system that sometimes caused errors when rendering transistor sizes which were specified in electrical models rather than by the automatic transistor finder.
- Fixed a bug that caused errors when exporting the active netlist in SPICE format with generic cells present.
- Fixed a bug when exporting project library cells in SPICE format which prevented the first .SUBCKT entry from displaying properly.
- Improved behavior of layer import feature when importing image formats which differ from that used by Pix2Net internally.
- Updated the Pix2Net manual.
- Added handling of “invalid states.” Users can now specify input values for cells which are not permitted by the design (for example, sending 0 to both S and R simultaneously on an SR-Latch). Specification of these invalid states will allow for correct truth table and Verilog output for affected cells.
- Added a CSV format option to the spectrometer export feature.
- Added support for optional “bulk” ports on MOSFET cells. If a bulk port is present, it will be shown in the schematic. If a MOSFET cell does not have a bulk port, then schematic will be drawn to represent the bulk tied to the source.
- Added display of transistor dimensions to the schematic window. For transistors not located by the automatic transistor finder, values entered as electrical properties will be used. This display can be toggled in the schematic context menu by right-clicking a schematic.
- Fixed a bug in the Cell Images export which caused it to stop early under some circumstances.
- Fixed a bug that prevented functional Verilog code from being written properly by the Library Cell export feature.
- Added a “complete netlist” export feature, which exports the component Verilog of the active netlist, followed by the functional Verilog of all the library cells, in one file.
- Updated the synchronization system to calculate backup directory sizes in the background, instead of delaying the appearance of the window until the calculation was complete.
- Added new safety checks to the synchronization system. It should no longer be possible to attempt to sync a project with anything other than satellite copies of that same project.
- Added a new Identify Cell tool to the Cell menu of the ribbon. This tool is able to identify many cells without the use of a reference cell library, and can rename the cell and its ports after making the identification.
- Fixed a bug that prevented the Truth Table and Netlist Text windows from updating automatically when Analyze Netlist was enabled or disabled.
- Test release for internal use.
- OR gates with more than 5 inputs are now correctly drawn with an extra connectivity bar.
- Tri-state ports are now treated as outputs for the purposes of state table display, schematic symbol display, and the "no outputs" netlist check error.
- Netlist error checking: A net with multiple tri-state ports will not cause a "shorted output" error.
- Fixed a netlisting bug related to net markers.
- Improved the error message for the "Clone Polygon" command.
- Added an extra check to the process of adding a sync project that prevents the user from moving forward with an invalid path.
- Fixed a bug that showed "Use GPU" as disabled but checked in the case that CUDA 8 is not installed.
- In Cell Search settings, users can now check “Verify orientation”. If this option is selected, then pix2net will use the relationship between the VSS and VDD ports and the well polygons in order to make sure that instances are always added in the correct orientation.
- The neural network feature now allows images to be scaled when extracting lines.
- Fixed a bug that prevented transmission gates from being detected in certain situations.
- Fixed a problem that caused the synchronize system to fail with large change sets.
- Fixed a graphical error with the select area tool.
- Fixed a bug with the select area tool which caused the selected area to be too small under certain circumstances.
- The cell search result viewer now pops up when results are found, and goes away when the results are committed or cleared.
- Added a context menu to the cell search results window.
- Fixed a bug in the "Import multiple images" feature that prevented images that were zero-indexed from being imported.
- Fixed the check that pix2net relies on to see if CUDA 8 is installed or not.
- Fixed a problem that prevented Pix2Net from working on computers that do not have CUDA 8 installed.
- The cell search system has been completely redesigned.
- Functional Verilog: Added semicolons to the end of NOT gate declarations.
- Functional Verilog: Fixed a problem that prevented cells with duplicate outputs from working correctly.
- Fixed bug with truth table generation that caused errors recognizing dupe/inverse columns with indeterminate values.
- Improved the neural network code that performs via extraction.
- Improved the safety of the synchronization process. For example, the sync operation will now verify that a .prj file exists.
- The sync system can now perform an automatic restore.
- The panel for exporting library cells now has a toggle all button.
- Fixed a bug that caused the 'Add Line' tool to go into a bad state if the user clicked multiple times without moving the mouse.
- Fixed a problem that caused 'Import multiple images' to skip files that don't have numeric characters in them, instead of stopping the import if it finds one.
- Fixed a bug that caused the 'Update Netlist' command to throw an exception in some cases.
- The Technology window has been modified so that all metal and via layers can be specified in the technology window. The technology window can now be filled out extremely quickly by using the “auto-assign” button.
- The user can now specify “Library Cell” or “Circuit Block” in the “Create Netlist”/“Netlist Connections” window, in order to automatically generate the netlist connections from the settings in the Technology window.
- Added options to the feature that exports a library cell catalog.
- Added the ability to export a library cell catalog.
- The truth table and functional verilog generators now work correctly with combinatorial cells that have multiple outputs.
- Added a feature for deleting all of the ports in a cell.
- The spice simulator now uses the correct length and width when simulating transistors, instead of using generic numbers.
- Short finder: Fixed a bug that caused an exception in the renderer when the focused polygon was deleted.
- Schematic: The "Go up a level" command now takes the user to the schematic block that contains the netlisted cell.
- Schematic: Added a "Add connected components to this block" option to the context menu.
- The short finder now allows the user to filter by layer.
- Active Nets: Added a "Append cells to schematic block" feature that is available from the context menu in the ports window.
- The schematic will now show a visualization of the selected state in the truth table window.
- Fixed a bug that allowed the user to run the short finder tool on a disabled netlist.
- Schematic: Fixed a bug that sometimes caused a null pointer exception during the loading process.
- Fixed a bug that caused the netlisting process to fail on large netlists.
- Added a feature to the “Edit Search Plan” window for deleting cell instances.
- Improved the accuracy of the truth table and functional Verilog output.
- Truth tables are now generated from the same engine that is responsible for the functional Verilog output.
- Schematic: Fixed a bug that allowed an invalid transmission gate to be detected.
- Truth table: Added a feature that allows the user to see the shortest possible path to a transition.
- Find External Ports: Pix2Net will now check the parent netlist in order to see if the VSS/VDD nets have been labeled. If they have, then that information will be used to find the VSS/VDD ports; if not, then Pix2Net will fall back to assuming the two biggest m1 polygons are the voltage sources.
- Fixed a bug that caused some polygon editing to update the generated layers in an incorrect way.
- Fixed a bug that prevented some polygon operations from working correctly.
- Schematic: Fixed a bug that allowed an inverter to be detected that had its output port wired to its input port.
- Schematic: Fixed a bug that caused some of the rotated text to have the incorrect size.
- Fixed a bug that prevented “Add cell to reference library” from working.
- Fixed a bug that caused a library cell’s netlist to get messed up in some situations when editing polygons.
- Cell search: The user can now specify the name in the “Add Cell” feature.
- Fixed a bug that prevented the user from canceling the netlisting process during the transistor detection phase.
- Added an 'Add Cell' option to the context menu in the cell search result window.
- Fixed a bug that caused netlisting to fail in certain cases with the error “Boundary nets and source nets not distinct”
- Fixed a bug that prevented ‘synchronize’ from working correctly with cell operations.
- Cell Search: Fixed a bug in the 'Add Bookmark' feature.
- Cell search: The "Score" column is now the average of the layer scores.
- Cell search: The user can now add a bookmark by right-clicking on a search result.
- Fixed a bug that caused the ends of some polygons to be chopped off, due to the “minimum polygon size” being applied at the wrong time.
- Fixed a bug that caused the extraction results from full and partial feature extractions to be slightly different.
- Fixed a bug in the cell search feature that caused a null pointer exception when scanning areas outside of the image layer.
- Fixed a bug in the cell search tool that incorrectly generated a "The search bounds must be within the boundary of the active netlist" message.
- Fixed a bug that allowed the netlist to get into a bad state in certain situations.
- Fixed a bug that prevented users from disabling a neural network in the feature extraction settings.
- Added a path step walker to the short finder. Users can now click through a table of polygons and their layers to step through a traced path. The overlay will move to and highlight the selected polygon, while dimming the rest of the path.
- Fixed a bug that caused Pix2Net to fail to start with a “Can't find dependent libraries” error.
- Upgraded the version of CUDA that Pix2Net uses to CUDA 8.0.
- Upgraded the version of OpenCV that Pix2Net uses to OpenCV 3.1.
- The schematic rendering system has been heavily modified so that schematic rendering is now much smoother, and the text looks sharper when you zoom in on it.
- Fixed some bugs in the schematic loader that caused null pointer exceptions when dealing with the ‘no connect’ and ‘supply short’ symbols.
- Fixed a serious bug that caused a netlist reset to also reset the associated schematic. Now that this bug is fixed, users can once again clear a netlist and re-run it without losing their schematic layout.
- Fixed a bug in the new transistor code that caused bad nets to be created during the netlisting process.
- Fixed a bug in the schematic window that caused a null pointer exception in some cases.
- Fixed a bug that caused netlisting errors.
- Fixed: The ‘Find External Ports’ feature was incorrectly adding external ports to nets in cases where a polysilicon or a diffusion polygon left the cell’s bounding box.
- Added a ‘Detect transistors’ flag to ‘Create Netlist’, which automatically detects transistors during the netlisting process. The transistors will be automatically updated whenever
the user changes the poly, diffusion, or well layers.
- Removed the old ‘Find Transistors’ functionality.
- Added a new option for finding library cell ports to the “Find External Ports” feature.
- Fixed a bug that prevented the viewer version of Pix2Net from starting.
- Fixed a bug in the neural network training process.
- Fixed a bug in the neural network import feature.
- Added the ability to create “filter” neural networks for performing line extraction.
- Fixed a bug that caused the synchronize process to fail when multiple users edited the same polygon.
- The add square tool now shows preview lines, allows the preview to be dragged into place, and enters two-click mode with ctrl, for easy size adjustment.
- Fixed a bug that prevented the user from exporting the bits after using the memory extraction feature.
- The line tools now show full preview points, and holding shift can now generate a 45 degree line in addition to the old 90 degree lines.
- The line tools now allow an optional third click to set the line thickness. This behavior is triggered by holding the control key during use of the tool.
- Added a polygon line erase tool.
- Fixed a recently introduced bug in the Schematic system that caused some logical blocks to show the wrong port names.
- Undoable polygon commands are now stored in a much more efficient way. The inefficient storage of certain commands was causing problems during the synchronization process.
- Fixed an issue that was causing junk polygons to be created when using the ‘Clone Polygon Area’ tool.
- Added the ability to export the active schematic as an EDIF file.
- In the clone polygon tool, the preview lines now stick to your cursor. This allows you to clone a polygon to a position that is far away from where you started without having to drag it there.
- Fixed a bug in the synchronize system that caused an ‘out of memory’ error when trying to apply a very large patch.
- Fixed a bug that caused a null pointer exception in the schematic when trying to load an inverter without an input port and an output port.
- Fixed a bug that prevented the schematic context menu from coming up when a block is selected.
- Added a freeform select polygon area tool.
- Fixed a bug in the code that renders the selected area bounds.
- Added a “Clone polygon area” feature.
- Bookmarks now store the zoom level, and bookmarks can now be synchronized.
- Schematic auto layout: Pix2Net will now find inverters and tri-state buffers in cases that involve transistors with their gates tied to voltage sources.
- Added a feature for fixing missing cell and port instances in the database.
- Prevented parallel transistor gates from being created from a mix of PMOS and NMOS transistors.
- Fixed a bug that caused a null pointer error while loading a schematic for a transistor without a source or drain port.
- Fixed a bug in the “Find External Ports” feature that prevented ports from being created in some cases.
- Inverters with multiple inverters are now called INV2X, INV4X, etc.
- Chains of inverters are now combined to INV3D, BUF4D, etc.
- The “Find External Ports” feature now uses the net names in the containing netlist when determining the names of new ports.
- Fixed a bug that caused a null pointer exception in “auto layout” mode in some situations.
- Changing the name of a net in the “Active Nets” window will now rename the ports in the schematic. Likewise, changing the name of a schematic port will update the name of the corresponding net.
- Fixed a bug in Block Manager that caused new blocks to always be created as children of TOP. New blocks will now be the children of the active block.
- The ports in the generated Functional Verilog code are now in the correct order.
- In the File tab, "Defragment Database" is now "Rebuild Database".
- Fixed a bug that prevented the “Select Polygon” tool from working.
- Fixed a problem that was causing netlisting errors when editing polygons.
- Fixed a bug that caused “Generate Diffusion” to unnecessarily regenerate all of the netlists in a project.
- Fixed a bug that caused “Find External Ports” to fail in some cases.
- Netlisting: The database structure has been dramatically changed. Ports are now stored and accessed in a much more efficient manner.
- Schematic: NAND and NOR gates are now combined with inverters to create AND and OR gates whenever possible.
- In the schematic “auto layout” mode, parallel PMOS and NMOS transistors are now combined into single gates (e.g. PMOS 2x, NMOS 4x, etc.)
- In the schematic “auto layout” mode, transmission gates are now detected in situations where the inverter is not inside the library cell.
- Fixed a bug that prevented the schematic from being saved correctly in certain situations.
- The ability to add new polygon layers is now disabled in synchronize mode.
- The delete key can now be used to delete the selected polygon, port, cell instance, anchor, or ruler in the overlay. If multiple types of objects are selected, then Pix2Net will ask you to specify which type you want to delete.
- Fixed a bug, which was accidentally introduced in the last version, that causes the images to disappear when you zoom all the way in.
- Fixed: The GUI no longer becomes unresponsive for a few seconds when selecting a large layer.
- Fixed a bug in 'Find External Ports' that prevented Pix2Net from finding all of the external ports.
- Fixed a bug in the code that generates functional Verilog.
- Fixed a bug that caused an error when trying to generate “Functional Verilog” for inverters and buffers.
- The “Find Transistor” feature no longer complains about multiple VSS/VDD ports.
- A friendly error message is now displayed if the user tries to add a hierarchical block in auto layout mode.
- A friendly error message is now displayed if the user tries to look at the schematic of a disabled netlist.
- Improved the way that netlisting errors are handled.
- Fixed a bug that caused an exception when trying to display an inverter with a missing input in the schematic.
- Fixed a bug that prevented the schematic from loading in certain cases.
- SpotCamera now allows the user to set the gamma adjustment.
- The “Find Transistors” feature will now do a better job of ignoring tiny polygon fragments.
- The “Find Transistors” feature will now warn the user if the VDD/VSS placement is ambiguous.
- The truth table compaction algorithm has been significantly improved.
- The “Netlist Connections” window now ensures that the columns are always wide enough to display long layer names.
- The “General Diffusion” command can now be run on a selected cell instance.
- The “Pair Inputs” feature can now be accessed in the “Project Cells” window, instead of in the “Truth Table” window.
- Pix2Net now automatically generates the “Functional Verilog” output in the “Netlist Text” window. The old text is still available under “H Functional Verilog”.
- In the overlay, the cell and port text is now a fixed size in microns. The text size can be adjusted in the “Cell Visibility” window.
- In the overlay, the cells and ports are now drawn far more efficiently.
- Fixed a bug in PostgresMgr that caused a “conversion between WIN1251 and WIN1252 is not supported” on non-English operating systems error.
- Recompiled asi_serial.dll using visual studio 2015.
- Added visual studio redist 2013 and 2015 to the installer.
- Add white balance options to the SpotCamera.
- The user can no longer select the Huntron stage and camera.
- Fixed a serious bug in the ‘Capture’ process that allowed an image to be captured before the stage finished moving.
- Fixed a bug in the code that controls a Spot camera.
- Fixed a bug that prevented Pix2Net from creating a database with the Windows-1251 character set.
- Fixed a bug that caused problems whenever a minor error occurred during the feature extraction process.
- Fixed a few bugs in the KiCad exporter.
- Fixed a bug that caused feature extraction to slow down dramatically on some layers.
- Fixed a bug that caused a null pointer exception during the feature extraction process.
- Added an “Allow Gaps” option to the “Import Multiple Images” feature, so that users can import layers with missing images.
- The memory usage for the spectrum layers has been greatly reduced.
- The underlying code that controls the stage, camera, and spectrometer devices has been cleaned up.
- The spectrum system now saves memory by storing the data points as 32-bit numbers, instead of 64-bit numbers.
- The stitcher now does a better job of placing tiles for large layers.
- The spectrometer capture process now runs significantly faster, because it moves the stage continuously, instead of starting and stopping at each pixel.
- Fixed a bug in feature extraction that caused an excessive amount of memory to be used at the end of the extraction process.
- Fixed a bug in the ‘Import layers from an existing Pix2Net Project’ feature that caused the layer indexes to get messed up.
- Training Set Manager: If the user adds a new training image, then that will now be the selected image when the window appears.
- Fixed a bug that was causing Pix2Net to load the wrong DLL files in some cases.
- Added support for the Mercury M-403.42S stage.
- Lowered the stage poll time from 500ms to 100ms.
- The spectrometer now uses a new API that is faster and more stable.
- The ODB++ export feature now includes the netlist in the exported file.
- In the Netlist tab, replaced "Netlist Properties" with three buttons: "Show Schematic", "Truth Table", and "Netlist Text".
- Fixed a bug that was causing syntax errors when exporting the netlist into a Verilog text file.
- Added the ability to export a project to ODB++.
- Neural network: Fixed some rounding errors that caused the vias to be off center.
- Neural network: The learning rate can now be specified.
- The neural network system for via extraction has been dramatically improved. You can now train a neural network that is extremely accurate and robust, but you must have a CUDA-capable graphics card, such as an Nvidida GeForce card, to use this new system.
- Pix2Net will now extract gate-level functional code in the “Functional Verilog” view. The existing functional code will now be shown in “H Functional Verilog”.
- The maximum amount of ram that Pix2Net can use (specified in “Pix2Net.l4j.ini”) is now based on the amount of ram that your computer has.
- Updated the documentation.
- Fixed a few bugs in the spectrum layer viewer.
- Changed the maximum java machine memory from 2 gb to 4 gb.
- Fixed a bug in the “image conversion” feature that was causing it to run extremely slowly.
- The layer merge command can now be combined with the 'Select Area' tool to create a smaller layer.
- The 'synchronize' command now makes separate tasks for copying the 'images' folder and the 'data'/'archive' folders.
- The synchronize feature now includes the 'images' folder when it copies the master project to the cloned projects.
- Added a “Log Debug Info” check box to the stage panel.
- The "Import Multiple Images" feature now works with the "raw" file format.
- Improved the features related to capturing images with the spectrometer.
- Pix2Net now requires Java 8.
- The "Import multiple images" feature now supports "Right-to-left" order and an arbitrary starting index.
- Fixed a bug that prevented layers from being imported.
- Made various improvements to the tools for working with spectrum layers.
- Added the ability to capture an image using a spectrometer.
- Fixed a bug that caused an error when creating a new project after closing another project.
- The “Find Transistors” feature can now find horizontal and vertical transistors in the same cell.
- Fixed a bug that caused “Find Transistors” to create a new transistor in situations where it should have used an existing transistor.
- Fixed a bug in the schematic view that caused “auto layout” to cause a null pointer exception in some situations.
- The "Non-Overlapping Tiles" export option now allows the user to specify a custom pixel size in nm.
- The user can now force the calibrate tool to be orthogonal by holding down the shift key.
- The "Place Components Using Physical Locations" operation now gives the user a friendly error message if the schematic contains hierarchical blocks.
- Increased the number of lines that can be drawn in the schematic.
- Added a 'Create block from selected net' option to the context menu in Block Manager.
- Fixed a bug that caused an unnecessary horizontal scroll bar to appear in the 'Layers' window.
- Fixed a bug in the netlister that, in certain situations, caused connected polygons to be placed into separate nets, instead of a single net.
- The Non-Overlapping Export feature now takes advantage of all the cores in the user's machine.
- Fixed a bug that prevented the “Short Finder” from rendering the shorted path correctly.
- The arrow in the PNP schematic symbol is now drawn in the correct position and orientation.
- Renamed the "Netlist Cell Instances" button to "Cell Instance Search", and moved it to the "Cell" tab.
- Moved the "Logic Block Search" button to the "Schematic" tab.
- Added a “Fix Port Polygons” option to the context menu in the “Netlist Browser” window.
- The Synchronize window now gives the user the option of clearing and regenerating the netlist during the synchronization process.
- The "Active Nets" window now displays more information about ignored errors.
- The "Clear Netlist" command now enables the top netlist, as well as the other netlists, if the user chooses the "Enable" option.
- Added a "Block Nets" window, which only shows the nets in the schematic block that the user is currently viewing.
- Added a "Retrace path" feature in the Short Finder.
- During the synchronization process, Pix2Net will now automatically retry a file copy if a "device is not ready" exception occurs.
- Redesigned the Synchronize window. From now on, the user simply has to define a list of the projects they want to synchronize with, and then press 'Run'. Pix2Net will automatically execute all of the steps required to do the entire synchronization process.
- Fixed a bug that caused synchronization to fail if a patch attempts to flip a cell that no longer exists in the master project.
- Fixed an error in the new block manager which caused null pointer exceptions when selecting a cell before any schematic had been loaded.
- In the Synchronize window, the user can now create a patch from all of the commands by clicking 'Create Patch' without selecting a branch.
- Fixed a display bug in block manager which caused the check box to shift too far to the right under certain circumstances.
- The Block Manager now shows the blocks as a tree, instead of a flat list.
- Removed the "Schematic Image" feature, because it is no longer used.
- In the schematic, fixed a bug that sometimes caused extra external ports to be incorrectly added to a schematic block.
- Fixed a bug that prevented "Save schematic" and "Load schematic" from working with schematics in the reference library.
- Fixed a bug that prevented the user from using "Load Schematic" with .sql files that were saved with versions older than 1.07.39.
- If the user makes changes to a schematic in "auto layout" mode, those changes will now be saved.
- Fixed a bug that was causing schematic errors in certain situations where the "no connect" or "supply short" symbol was present.
- Added a "Stitch After Import" checkbox to the "FEI Maps" and "Multiple Image" imports.
- Fixed a bug that prevented the "FEI Maps" import feature from working.
- Fixed a bad setting in the "postgresql.conf" file that was causing the "pg_xlog" directory to get way too big.
- Fixed a bug that caused an error when the user attempted to view a schematic with “Analyze Netlist” turned off.
- Fixed a recently introduced bug that caused some truth tables to be generated incorrectly.
- Fixed a TopologyException that sometimes occurred when dealing with overlapping polygons in a generated polygon layer.
- Changed the Alignment Review system to have better coverage on non-square review areas.
- The schematic layout system has been redesigned in a way that results in much better port placement in both manual mode and auto layout mode.
- In the schematic, fixed a bug that sometimes caused the VDD and VSS schematic symbols to have the wrong orientation.
- Improved the gate identification code so that the AND gates and OR gates in some cells, such as the XNOR3MVOTE3 cell in the reference library, are now correctly detected.
- Fixed a bug in feature extraction that sometimes caused a “Ring has fewer than 3 points” error.
- Added the ability to save the contents of the Logic Paths window to an XML file, and to restore the logic paths from an XML file. To use this feature, right-click in the Logic Paths window and use the “Load Paths” and “Save Paths” commands in the context menu.
- Fixed a bug in the “Save schematic as image” feature that was causing the top of the image to be cut off in some cases.
- Added the ability to save a schematic page as an image. The resolution of the saved image will be based on the user’s current zoom level.
- Added more options to the “Settings” dialog in the “Stitch Manager”.
- Fixed a bug that was causing invalid truth tables to be generated for latches.
- Fixed a recently introduced bug that prevented new projects from being created.
- Fixed a bug that prevented layer fusion from working with 24-bit png files.
- Fixed a bug that prevented some types of tif files from being imported in “Import multiple images”.
- In the “Stitch Settings” dialog, the user can now control the minimum correlation used in pass 2 and the max slice length used in pass 3.
- Fixed a bug that prevented the user from changing the name and type of external ports in the schematic view.
- In the auto-layout schematic mode, nors and nands that share transistors will now be correctly identified.
- Schematic: In auto-layout mode, transmission gates and tristate inverters are now detected automatically.
- Changed the “Regenerate Diffusion” button to a “Generate Diffusion” button. From now on, users only need to click “Generate Diffusion” once per project. The generated diffusion layer is automatically kept up-to-date whenever the user edits the polysilicon or diffusion layers.
- Changed “Device Properties” to “Technology” and moved it to the Cells tab.
- Added the most commonly used buttons for identifying cells (Generate Diffusion, Find Transistors, etc.) to the Cells tab.
- Schematic: Fixed a bug that caused some logical block names and positions to get reset when combining multiple logical blocks into the same parent block.
- BlockManager: Added the ability to combine multiple logic blocks into a single parent block
- Export: Fixed a bug that caused the "Library Cell Netlists" export feature to skip some of the library cells in the project.
- Schematic: Fixed a bug that caused "Load schematic" to fail in some situations.
- Capture: Fixed a bug that was causing a "Focus adjustment schedule cannot be created" error in some situations.
- Netlist exporting: Fixed a bug that caused the net names to be incorrect when exporting a netlist with the schematic block hierarchy.
- Fixed a bug that was slowing down Pix2Net's communication with the Pix2Net Server.
- In the schematic window, fixed a bug that caused "Place Components Using Physical Layouts" to fail in some situations.
- The "Find Transistors" feature now finds transistors by intersecting the polysilicon and diffusion layers, instead of using a more complicated algorithm.
- Divided the netlist export windows into "Active Netlist" and "Library Cell Netlists".
- The "Active Netlist" export window can now be configured to export a hierarchical netlist using schematic blocks.
- Improved the algorithm that removes extra bumps from lines in the schematic.
- Improved the stitching algorithm.
- Capture Config: Changed the focus settings so that users can now create a "focus adjustment schedule" from a set of sampled focus points.
- Manual Move: Added some simple controls for making focus adjustments. This is the easiest way to add sampled focus points to an area in the Capture Config window.
- Command History: The information that is displayed for the polygon modification commands ("Add Rectangle", "Erase Rectangle", etc.) is now much more detailed. The additional information includes the layer ids and the bounding boxes of the added/removed polygons.
- In the schematic, fixed a bug that caused external inputs and outputs to be drawn incorrectly when rotated 90 degrees.
- In the schematic, Pix2Net is now smart enough to route nets through empty cell lanes in some situations, instead of only using the wire lanes. This removes the very annoying extra bump that sometimes shows up when connected components are not right next to each other.
- Fixed a bug that caused an error message to be displayed when trying to recapture images on a layer that has already been completed.
- If a schematic component is rotated, the text is now rotated as well.
- In the schematic, a "No connect' symbol is now drawn if a port is not connected to any other ports.
- In the schematic, a "Supply short" label is now drawn if a port is connected to a net that has VSS and VDD shorted together.
- The "Import" button in the "File" tab now brings up a friendly GUI.
- The import tasks now run in the background.
- Fixed a bug that prevented the "Import from single image" feature from working with large images.
- Added a feature for importing FEI Maps as Pix2Net layers.
- Fixed a few bugs that allowed the Block Manager and the Schematic window to become unsynchronized.
- Logic Block Search: Added an "Exists In" column that tells the user which schematic block each cell instance is in.
- Logic Block Search: Added a "Save as Schematic Blocks" button that allows the user to quickly save all of the search results as schematic blocks.
- Logic block search: The user can now import the pattern to search for from a schematic block.
- Logic block search: The user can now group cells together during this search. For example, if the user has multiple AND cells with differing ids, they can now treat those AND cells as equivalent cells during the search.
- Fixed a bug that was causing schematics in large projects to load very slowly.
- If a schematic has more than 1000 nets, the lines for the nets will no longer be drawn, because routing that many lines takes too long.
- Fixed a bug that caused the current schematic page to revert to the top schematic page whenever the netlist was modified.
- Fixed a bug in feature extraction that caused extraction errors in certain situations.
- The logic block search is now much faster when dealing with large netlists. A search that was previously taking 45 minutes, with no end in sight, now takes just 5 seconds. The speed increase was achieved by doing a much better job of filtering out the irrelevant nets from the graph that is fed into the algorithm that searches for subgraph isomorphisms.
- Fixed a bug that caused the overlay to zoom to the selected cell whenever the user added a new cell or new cell instance.
- Fixed a bug that caused the overlay to zoom to the selected net whenever the netlist was updated.
- Import multiple images: Added an "Ignore Prefix" field, which allows the user to specify a prefix for each filename that should be ignored. For example, if every filename is of the form "abc123_x_y.png", the user can now set "abc123" as the prefix to prevent "123" from being used as the x coordinate.
- The feature extraction process no longer creates overlapping polygons along tile boundaries.
- The feature extraction process now takes advantage of all of the available cores on the user's machine.
- The feature extraction process now does a better job of identifying fill blocks along tile boundaries.
- Fixed a bug in the "Clone cell polygons" feature that prevented polygons from being cloned to some cell instances.
- Added "Pass 1 Settings" to the "Stitch Settings" dialog. This allows the user to tweak the settings that are used during the first stitching pass.
- The editing of electrical models and the entire schematic tab are now disabled in "Synchronize" mode.
- If you select a net or cell in the overlay, the schematic window will now automatically zoom to the selected net or cell. Likewise, if you select a net or cell in the schematic, the overlay window will now automatically zoom to the selected net or cell. If you select a net or cell outside of the overlay/schematic window (e.g. clicking on a net in the Active Nets window), then both the overlay window and the schematic window will automatically zoom to the selected net or cell.
- Fixed a recently introduced bug that prevented the user from selecting multiple cells in the schematic window.
- In the template editor window, the user can now enable a "condensed log file" option (the user can also change this option in the "project properties" window). When this option is enabled, pix2net will save capture logs to a condensed log file after each run.
- Schematic: Renamed "Block Creator" to "Block Manager", and added three new buttons: "Append cells to block", "Remove cells from block", and "Go to block".
- Import layer from multiple images: Added a 'Split' tab, which allows the user to split every imported tile along the X and Y axis. For example, splitting each tile by a factor of 3 would turn every imported tile into 9 smaller tiles.
- The feature extraction window now defaults to the first visible layer as the target layer, and sets the tile index to the tile that the user is currently looking at in the overlay.
- A friendly error message is now displayed if the user tries to resize the cell in an invalid way.
- Fixed a long-standing bug that sometimes caused an error while rendering polygons.
- In the "Reference Cells" window, added a "Duplicate truth table finder" button, which opens a window that groups reference cells with matching truth tables together.
- In the "View" tab, added a "Memory usage" button, which opens a window that shows the amount of java memory that the Pix2Net application is currently using.
- Fixed a bug that prevented the user from copying certain cells into the reference library.
- Added a "Clone Cell Polygons" command to the "Cells" tab.
- The tools that draw rectangles as the user drags the mouse (e.g. Select Area, Add Rectangle, Erase Rectangle, etc.) no longer cause the polygons to be constantly redrawn during the dragging. Also, a friendly error will now be displayed if the user attempts to use one of these rectangle-drawing tools in an invalid way (e.g. if the user tries to erase a rectangle, but the active polygon layer is not visible).
- Improved the performance of the polygon renderer.
- Fixed a bug that prevented some truth tables from being updated after a netlist modification.
- Made a tweak to the stitcher that dramatically improves the results on some layers.
- In the reference library, truth tables that have been imported from a file will now be displayed correctly.
- Corrected a bug in the Identify by Truth Table feature which caused lots of error messages during reference library state table generation.
- The Cell Identifier window now provides more feedback during the state table generation process.
- Pix2Net now uses ngspice to simulate circuits, which dramatically improves the accuracy of the truth tables that Pix2Net generates.
- The keyboard keys used to navigate in the Overlay (a, s, w, d, q, e) will now work in the Schematic and Stitch windows as well.
- Fixed a bug that caused layer importing to run very slowly on certain computers.
- The stitcher now adjusts the broad search parameters automatically when stitching layers that have unusual overlap settings (e.g. 30%).
- The layer importer no longer throws an error because of an unexpected subdirectory or hidden file (e.g. thumbs.db).
- Stitching: Fixed a bug that caused some broad searches to report search results as valid in cases where those results were in fact invalid.
- Stitching: The "Hide errors along border pairs" setting now defaults to false. This setting is nice in situations where the edge of the layer represents the edge of a device and contains a lot of charging effects. However, this setting should still start in "off" mode, so that the verification errors won't be hidden from the user.
- Stitching: Running a broad search manually will now automatically overwrite the pass 1 result. The broad search will also clear the pass 2 and 3 results in the associated row or column, because the pass 2 and 3 results for that row/column are now out of date.
- The BJT schematic symbol now supports BJTs with multiple emitters and/or collectors.
- Fixed a bug in "Import layer from existing project" that messed up the layer indexes in certain situations.
- Updated the stitching documentation.
- Fixed a race condition in the multiscale generation code.
- Updated the documentation.
- In the "Export" window, added an option to export "Overlapping Tiles" for the selected layers. If an area has been selected using the "Select Area" tool, then only the parts of the layer that are touching the selected area will be exported. A file called "overlapping_tiles.xml" will be generated, which contains general information about each exported layer.
- In the "Import" menu, added an option to import "Multiple layers from images". If you select this option, and then you select the "overlapping_tiles.xml", all of the exported layers and their capture history will automatically be imported into the project.
- Fixed some bugs in the new stitching system.
- Added a database upgrade that adds some properties to the PNP and NPN electrical models.
- The stitching system has been completely rewritten.
- Updated the documentation.
- In the schematic window's context menu, added a 'Save schematic' and 'Load schematic' feature. These options allow the user to save a schematic (in manual layout mode) to a text file, and to restore a schematic from a text file.
- The "Feature Extraction" window now has a button for saving a copy of the preview image.
- Anchor tools: Fixed a warp grid bug that sometimes caused a "matrix is singular" error when dealing with coordinates on the millimeter scale.
- Fixed a recently introduced bug with moving ports which prevented ports in TOP from being moved at all.
- Selected ports are now rendered even if the camera is zoomed out far enough to hide ports.
- You no longer need to change to the ‘Move’ tool to move ports in the overlay. Instead, as long as the ‘Select Cell’ tool is active, you can move ports around by just clicking and dragging.
- Schematic window: You can now put the selection tool in ‘toggle mode’ by holding down the ctrl key as you click.
- Fixed: Ports can no longer be moved outside of the bounds of their cell.
- Fixed: The cell resize tool can no longer be used to move a port outside of the cell bounds. It now also responds as expected to a cancel command from the escape key.
- The documentation has been updated.
- The “Add Cell” dialog now includes VSS and VDD ports on high-level cells. It also defaults the port layer to the layer selected in the “Layers” window.
- The “Add Cell” dialog now has the “Generic” type selected by default.
- In the “Edit” command, in the context menu in the schematic, fixed a bug that caused an SQL error message.
- A cell’s schematic symbol is now determined by the cell’s electrical model.
- The “Add Cell” feature now brings up a dialog that asks the user for the cell name, cell instance name, and the electrical model. An initial set of ports will also be suggested to the user, based on the selected electrical model. The user can also customize each port’s name, type, and layer.
- Removed the concept of the “Digital Cell” electrical type, because it is no longer needed.
- In the ‘Anchor Group Settings’, the user can now specify if ‘Align Anchors’ should be performed after each ‘Add Anchor’. This option should usually be turned on, but you can turn it off if the ‘Align Anchors’ process is taking too long.
- Added “Raith Stage” as a new stage that the user can connect to.
- Updated the documentation.
- Fixed a bug that allowed invalid warp grids to be saved to the database in certain situations.
- In the cell instance search feature, the wildcard character (“*”) will now match spaces. So, if you specify “cell*” as your search string, that will match names with spaces, such as “cell 123”.
- The non-overlapping export feature now uses the properties defined in the project template when it creates the 'area.xml' file.
- A friendly error message will now be displayed if the user attempts to create a project in an existing, non-empty directory.
- Fixed a bug that prevented some schematics from loading correctly in auto layout mode.
- The grow operation will no longer add rounded corners to the grown polygons.
- The shrink operation will now union polygons before shrinking them, so that contiguous polygons are shrunk correctly.
- Fixed a problem in most of the polygon operations that prevented the last batch of polygons from being processed correctly.
- Fixed a problem in the 'Stitch' process that sometimes caused a null pointer exception on partially captured layers.
- Capture Config: Increased the upper limit of the 'Pixel Width' field to 1,000,000 nm per pixel.
- If the user moves polygons to a different layer, then those polygons will now be deselected (unless the selection mode is "Visible layers" and the polygons are still visible)
- The "Move polygons to layer" feature now remembers the last layer that the user specified.
- You can now import non-overlapping tiles with the “Import from multiple images” feature.
- When importing multiple images, the importer is now much more tolerant of different filenames, and it auto-detects if the filenames are 0-based or 1-based, and the image extension is auto detected as well.
- The user can now put the 'select polygon' tool into 'toggle mode' by holding down the 'ctrl' key.
- The “Golden Comparison” GUI now allows you to save the setup for each comparison you do, so that they can be re-run easily. It also allows you to use an “ignore layer” to define areas that you want the comparison algorithm to ignore. The bug that caused it to report the same error multiple times has been fixed.
- Added “XOR” to the Polygon Operations. This operation will create a new layer that consists of the polygons in layer A that do not touch layer B, and the polygons in layer B that do not touch layer A. The new layer will not contain any partial polygons from layer A or layer B.
- In the “Schematic” tab, added a “Schematic Net Browser” window. When you select a net, this window will show you the “net tree”, which is all of the nets in the other netlists that are connected to the selected net. You can then double-click on a port in order to travel to a different netlist.
- Added an option to the schematic context menu called “Place components using physical layout”. This feature will ask you for a grid size in microns. The grid size is an aesthetic choice: If the value is too low, your components will have too much space between them; if the value is too high, your components will be squeezed together.
- Schematic symbols will no longer be set if the cell does not meet the port requirements. For example, if you have an electrical model, but your inductor has 5 ports instead of the expected 2 inout ports, then the inductor symbol will not be automatically set for that component.
- GDSII export: Fixed a bug that sometimes generated an invalid polygon when rounding the coordinates to whole numbers.
- GDSII import: Fixed a bug that caused the import process to stop on a particular error, instead of just reporting the error and loading the rest of the file.
- Fixed a bug that caused an exception when using automatic layout mode with a schematic that contains non-transistors.
- When a component is added to a schematic, that component’s electrical model is now used to determine the initial schematic symbol.
- Made the netlisting code a little more robust: It will now detect a particular type of database problem and automatically fix it.
- Setup Server: In a protocol, you can now add a custom script that can be executed when a script step fails. This is useful if a script step fails in such a way that the SEM is left in live mode; your ‘on failure script’ can take over in this case and put the SEM back into paused mode, so that the next time Pix2Net retries the script, it will work.
- Fixed a bug in the GDSII export that caused a few polygons to get dropped as their precision was reduced to 1 nm.
- The ‘Go to coordinate’ command has been improved:
- You can now bind a shortcut key to this command
- You can now fill in each field in the dialog by simply using ‘tab’ and ‘enter’ on the keyboard, so that you don’t have to touch the mouse
- The 5 most recent locations are now saved
- The “Generate Multiscale” operation, and the “Stitch” and “Verify Stitch” stages of the stitching pipeline, will now take advantage of all of the cores on your machine, so you should see some pretty big speed ups.
- Fixed a bug that prevented the user from being able to cancel “Generate Multiscale”.
- Added a template system. Templates can be used to add fields for a user to enter when creating a new project or capturing a new layer. These fields can then be exported from the “Capture History” window.
- Additional information is now logged for each layer, such as when the run was started, when the run finished, how much time was spent moving the stage, how much time was spent auto-focusing, and how much time was spent capturing images.
- The “Capture Config” window has been redesigned.
- The “Capture History” window has been redesigned.
- Added two new tutorials:
- “Capturing a Layer” describes the steps for setting up and starting a run.
- “Logging Additional Information” explains how to use the new template system.
- Improved the proximity check. It should now find the proximity problems that it missed previously, such as polygons that contain holes with edges that are too close together.
- The polygon thinness check will now flag extremely small polygons. Previously, it was flagging polygons that were only thin in certain areas, but it missed the polygons that were thin all around.
- Removed the Stitch Advice dialog.
- Fixed a bug in the 'Import layer from existing project' feature that caused an error when importing certain layers.
- GDSII exporting: Improved the way that polygons are processed during the GDSII export process.
- Polygon Operations: Added a new operation for reducing the precision of polygon coordinates.
- Stitch grids now load much, much faster when you change to the "Select Stitch" tool.
- Fixed a bug in the stitch editor that caused a null pointer exception when one of the images was missing.
- The stitching pipeline now works correctly in a situation where a layer has only been partially captured.
- Added a feature to the stitch editor that generates points for empty edges. This is useful if you want to run 'Generate Grid' on the new tiles you've added, but you don't to lose the stitching that you've already done.
- Polygon subtraction now deals with problematic polygons in a more robust way.
- In the schematic view, the "Go into cell" and "Go up a level" commands can now be used to navigate through different netlists.
- Stitching: "Generate Grid" no longer fails to run if there are too many missing images.
- Added a confirmation prompt to the 'reset layout' command in the schematic context menu.
- Netlist checks: The Database consistency check now checks for duplicate port instances in the database.
- Fixed a bug that caused the schematic to fail to load when processing certain VSS/VDD nets.
- Capture config: Added the ability to set the amount to rewind the focus after each row. This greatly reduces the chance that pix2net will fail to adjust the focus at the beginning of each row.
- Added the ability to delete ports from the cell instances window
- Added the ability to convert a "Section" cell back into a normal cell.
- In the "Project Cells" window, the "Show netlisted [cell name] and children" has been changed into a "Move into [cell name] netlist" option. This is the equivalent of pressing the green down arrow to change the active netlist to the selected cell.
- The "Top" cell can no longer be accidentally deleted by the user.
- Fixed a bug in "Select Net": If the user clicked on a polygon that was in multiple netlists, and the user was not currently in the deepest netlist, then the user was prompted to switch to the deepest netlist. From now on, the user will only be prompted to switch to a different netlist if the polygon they are clicking on is not in their active netlist.
- Fixed a bug that caused "Thickness Check" to fail to complete on certain layers.
- Fixed a bug that caused Pix2Net to run out of memory when starting a capture on a very big layer.
- Added a "metal thinning check" polygon operation. This operation will generate a report highlighting areas where polygons are thinner than a user-specified value.
- In addition to the traditional rectangular tool, polygons may now be erased with a "drawable" tool similar to the add polygon tool.
- The report window now has the ability to delete multiple reports at the same time. To use this feature, select one or more lines in the report list, and click the delete button.
- Reports can now be "visualized" using a new button in the report window. During visualization, a new polygon layer will be created which shows the location that each report entry indicates.
- Added a polygon proximity check operation.
- Added 'Maximum' as a merge mode in the "Layer Merge" feature.
- Improved the netlisting performance.
- Feature extraction is now a trackable operation that can be used in 'Synchronize mode'.
- The "Layer Merge" command now allows the user to choose the way that they would like to blend the layers. The user could either overwrite all of the layers with the top-most layer, or they can choose to add all of the layers together.
- In the training image window, the size and color of each via can be adjusted.
- The "Active Region" tool can now be run on a selected cell, instead of always running on the top cell.
- The "Check Vias" tool now generates a new polygon layer that shows where every potentially misplaced via is.
- The "Check Vias" operation, in the "Polygon Operations" window, now works correctly.
- Fixed a bug that caused the netlisting code to fail to detect touching polygons in certain situations.
- The GDS export now replaces spaces with underscores for layer names.
- The "Find External Ports" feature now handles source, drain, and gate ports correctly.
- The command history view now has the concept of filters, a statistics button, and a description for the selected command.
- Added a "Via Check" feature, but we just found some bugs in it, so you may not want to run it until the next release.
- Fixed bugs in the "Export non-overlapping images" and the "Export single image" features.
- Fixed a bug in the polygon straightening tool.
- Added a "Eliminate Overlaps" polygon operation. This operation allows you to eliminate overlapping polygons by either unioning them together (which used to be call "union self") or by only keeping one of the overlapping polygons (this is great for removing vias).
- The schematic loader now prints a warning if it is unable to load a component's position.
- Added a "Mask" operation to the Polygon Operations window. This operation allows you to perform an action on every polygon in a "target layer" that overlaps a polygon in a "mask layer". The action can be "Move the polygon", "Copy the polygon", or "Remove the polygon". The condition can be "if the polygon is overlapping a mask polygon", or the condition can be "if the polygon is not overlapping any mask polygon".
- The "Aggressive" option has been removed from the Subtraction operation, because the "Mask" operation now provides that same functionality and more.
- The "Active Regions" command can now generate a report without actually generating transistors.
- Fixed a bug that caused "Active Regions" command to include too many active regions in its problem report.
- Fixed a bug that caused via extraction to null pointer on certain images.
- Fixed a bug in the schematic code that was causing a null pointer exception in certain situations.
- Added a "Active Regions" button to the "Cells" tab. This feature will add PMOS and NMOS transistors to all of the active regions in a project.
- Fixed a bug in the polygon operations that was causing Pix2Net to load way too many polygons in certain situations.
- The "Find Transistors" button now allows the user to specify a n-well or p-well layer.
- Added the ability to use a neural network to extract vias.
- In the polygon extraction window, the user can now create a ‘training image’, where they can label all of the correct vias. The user can then generate a ‘via report’, which will quickly tell the user why certain vias are missing and certain vias were incorrectly added. The user can use this via report to optimize their settings.
- Added an aggressive option to the subtraction polygon operation. If the 'aggressive' option is turned on, then the output of 'A - B' will only be the polygons in A that are not touching any polygons in B.
- The US locale is now set as the default locale.
- Fixed a bug that prevented new projects from being created.
- Added new settings to the via extractor. You can now set the ‘size tolerance’, so that vias that are too big/too small will not be added. You can also specify a ‘start edge’ and an ‘average edge’.
- The postgres database is now set to always run with US locale and messages.
- Fixed errors that were occurring on some layers during the polygon straightening process.
- Feature extraction: The via extractor now uses the “Edge intensity” setting to determine which edges are strong enough to possibly be vias, instead of trying to determine the threshold automatically.
- Added new options to via extraction. There is now an option to filter out vias with edges that are not intense enough, or vias that are not bright enough, or vias that are not circular enough.
- Added a feature for straightening polygons in the feature extraction window.
- The polygon operations window is now more user friendly.
- Added a “Polygon Alignment” button to the “Alignment” tab, which brings up a new “Polygon Alignment” window for keeping track of the alignment of polygon layers to image layers.
- A couple of features have been moved: If you right-click in the “Layers” window, you’ll no longer find “Warp polygons to image” (that has been moved to the Polygon Alignment” window), or “Synchronize Warp Grid” (that has been moved to the “Polygon Alignment” window) or “Identify Fill Blocks” (that has been moved to the “Polygon Operations” window).
- Fixed a bug that prevented the user from being able to rename certain nets.
- Fixed a bug that prevented “Import layer from single image” from working with a tiff file.
- Fixed a memory leak in the stitching code.
- Fixed a memory leak in the feature extraction code.
- The icons have been improved in the Project Cells window. From now on, you will see a little white document next to each netlisted cell, and a starred white document if the netlisted cell is the active netlist.
- In the schematic view, the VDD/VSS symbols are now locked to the component they are attached to. So, if you have a NMOS transistor connected to a VSS port, anything that you do to one (i.e. move, flip, rotate) will happen to both the NMOS transistor and the VSS port, so that they are always synchronized.
- Polygon Options: The polygon selection tool can now be set to select polygons in the active layer, or polygons in any visible polygon layer.
- Fixed: If the user deleted the selected polygons, Pix2Net did not actually clear its list of selected polygon ids, so the tools that operate on selected polygons were still enabled.
- The schematic no longer fails to display if a cell has too many ports for its schematic symbol (e.g. a resistor with 3 inout ports).
- A friendly error message is now displayed if the schematic fails to load due to a bad netlist. The error message will tell the user what they can do to repair the netlist.
- Fixed a few schematic bugs, including a bug that prevented the position of VSS/VDD ports from being saved correctly
- Updated the manual
- Fixed a bug that allowed the user to select “port polygons” using the polygon selection tool.
- Recovery System dialog: Added a “Rebuild database” option. This is a useful feature for trying to recover from a corrupt database. This feature will dump your database to a text file, and then recreate your database from that text file.
- Anchor group window: Added a feature that lets the user create a copy of an anchor group with a different stationary layer.
- Import multiple layers: Added a new filename pattern
- Feature extraction: Added the ability to filter out floating vias.
- Transform layer: Fixed a bug that caused the transformed anchor points to be slightly incorrect.
- Schematic: Fixed a bug that caused problems when dealing with nets that only have a single, external port.
- Added the polygon version of “Flip left to right”, “Flip top to bottom”, “Rotate clockwise”, and “Rotate counter clockwise” to the context menu. These commands are undoable.
- You can now transform multiple layers, and their associated anchors groups, by using the “Transform Layers” button in the “Image” tab.
- Fixed a bug that prevented the schematic from being loaded correctly in certain situations.
- Multiple schematic components can now be moved into the same grid cell, so long as the components are not overlapping.
- Fixed a problem in the “Layer Merge” tool that caused the merged layer to have too few columns and rows. The number of missing columns and rows increases with layer size, so the problem becomes more obvious on larger layers.
- A new schematic system has been integrated into Pix2Net. Users will now see the new schematic view for both library cells and higher-level netlists.
- Fixed a bug that prevented the ‘move’ tool from working with sections.
- The search button in the “Netlist Cell Instance” window now allows wildcard searching.
- Layer transformation: In prior versions, you were unable to rotate/flip a layer that had already been stitched. Now, you can rotate/flip a layer and the tiles will still be warped correctly, so you don’t have to re-stitch after the transformation.
- Stitching: The “Fix Point” feature now works better on tile pairs that have an outer stitch point, but not an inner stitch point.
- Cell search: Every search plan now has a target cell instance assigned to it at all times. This “target cell instance” is the cell instance that the search plan will search in by default. If the user attempts to search in an area outside of this cell instance, they will receive a friendly error message. Previously, the search plan would attempt to search in the selected cell, and that created a lot of confusion.
- Fixed a bug in the upgrade process that prevented the memory extraction project from upgrading.
- Users can no longer add an empty section with the “Add Section” tool.
- Fixed a bug that prevented the select tool from working with sections.
- Fixed a bug that prevented the ‘Move to active section’ command from working with certain sections.
- Cell search: If the user does a cell search, and then closes the results page without marking any results as valid or invalid, Pix2Net will now offer to delete those results for the user.
- Fixed a bug in the code that controls the MSI-1 stage.
- The user is now informed when the capture process is waiting for 5 minutes between the final three retries to capture an image. The user is given the option to force an immediate retry or to abort the capture process.
- Once the user starts capturing a layer, the capture settings for that layer can no longer be changed. An error message will be generated explaining the available options.
- You can now click "Capture History" in the layers window to see properties for all layers. Clicking edit from there allows editing of the editable fields for that layer.
- Capture errors no longer disable the current layer in the Capture Config dialog.
- Using the select net tool on a net outside the active netlist now offers the user the choice to switch to that netlist before processing the click.
- The warp grid is now automatically reset if the user re-stitches a layer, because the current warp grid becomes invalid as soon as the user re-stitches a layer.
- Updated the documentation for netlist properties.
- Added a "Detector" field to the capture config window. This field will appear in the area.xml file during the non-overlapping export command.
- Fixed an error that occurred when deleting an anchor group.
- The Pix2Net warp grid system has been overhauled. The old system would sometimes cause bad warping around the edges of a layer; the new system does not have this problem. Note: When projects are upgraded, Pix2Net will modify the existing anchor groups so that the old warp grid is expressed correctly in the new warp grid system. So, don’t worry if you see a new set of anchors in an old project.
- The annotate button in the “Netlist Cell Instances” window is now updated when the user goes in and out of synchronized mode.
- Users are now prevented from accidentally adding two cell instances exactly on top of each other.
- Users will now receive a friendly error message if they attempt to create a zero-size cell.
- Capture/Auto-focus will now automatically retry 5 times if it fails, with a 5 minute pause before each of the last three attempts.
- Auto-focus will now automatically retry 3 times if it fails.
- Fixed a bug that caused the number of columns and rows to be calculated incorrectly.
- Fixed a bug that caused an exception when the user tried to calculate columns and rows before initializing the stage and camera.
- Added a “Database Consistency Check” to the list of netlist checks. This check will go through your database and report every missing entry in the database that could cause a netlist to be invalid.
- Updated the manual
- The ‘Netlist Properties’ window, which previously consisted of 4 tabs (Netlist, Schematic, Auto-Schematic, Truth Table), has now been split into separate windows.
- The ‘Select Cell’ tool is now the default tool.
- You will now get a friendly error message when you try to open a project that was created with a newer version of Pix2Net (previously, the error message simply said ‘the database upgrade failed’).
- The stage configuration has been improved. Users can now assign controller axis 1, 2, and 3 to the X, Y, or rotation stage.
- Assign Module dialog: Pix2Net now uses the standard list of module files, instead of reading in all of the files in the 'modules' directory.
- Assign Module dialog: The user can now hit enter to do a search, instead of having to click the search button.
- KiCad exporting: Spaces are now removed from the cell names and port names.
- Improved error handling in the Pix2Net server.
- The user can now assign a module to each cell, for the purpose of exporting printed circuit board layouts to KiCad.
- The installer now adds a ‘License Status’ link to the start menu, so that users can easily check the status of their dongles.
- Image capturing: If you enable the image backup feature, images will now be backed up in the background process, so that the image capture process will not slow down
- Image capturing: You can now specify an “images” directory when you use the image backup feature, and the layer directories will automatically be created for you.
- Non-overlapping tile export: The layer capture properties will now be written to the area.xml file.
- Fixed bugs in Instance Consistency netlist check:
- Fixed bug that prevented proper operation when checking multiple netlists.
- Netlist check window no longer lists TOP. Table is now sortable, and defaults to sorting by cell name.
- Improved progress bar experience for instance consistency checking.
- Instance consistency checker now reports "second chance matches" if a failed netlist instead matches another cell which was searched.
- The documentation has been updated (Getting started and Tutorials).
- When exporting a KiCad .sch file, exporting a cache.lib file is now optional.
- When exporting a KiCad .cmp file, mounting holes are no longer treated like pins that need to be matched to ports.
- When exporting a KiCad .cmp file, cells with no electrical type are now compared to modules with names that start with “DIP” or “MIL”.
- Adjusted placement of the tooltip for the application log error icon. It should no longer cover the icon when P2N is maximized.
- You can now export the active netlist to a KiCad schematic file (.sch). For now, only the components are added to the schematic. The resistance is labeled on resistors, and the capacitance is labeled on capacitors.
- The netlist "move up" arrow now dives into the next netlist up its parental chain, setting visibility along the way, instead of always going straight to TOP.
- The Pix2Net server is now included in the installer.
- In the manual, added a "Setting up Auto-Focus" section to the "Capturing an Image" tutorial.
- When the user changes the active netlist, the new active netlist and its children are automatically made visible.
- When the user executes 'Find Transistors', the resulting transistors are automatically made visible.
- There is now a “Save” button in Logic Block Search, which you can click to save your results as a “pattern”. You can then click the “Load” button time to load as many patterns as you want in the search results window.
- Added an “Instance Consistency Check” to the “Netlist Checks” window. This feature will go to each instance of a cell, create a temporary netlist for that instance in memory, and verify that the netlist matches the netlist of the primary instance. A report will be generated that lists every instance that does not match the primary instance’s netlist.
- Synchronize: Fixed a bug that prevented branches from being removed.
- Synchronize: The user is now presented with a friendly "Nothing to do" message if they try to create a patch for a project with no new commands.
- Synchronize: The user is now presented with a confirmation dialog after clicking ‘Create Patch’. This confirmation dialog will tell the user if multiple users have worked on the project since the branch point (which probably means the branch point is incorrect).